| |
|
Welcome to our DesignLine network of web communities. On these sites, we provide practical how-to technical information for engineers and engineering managers involved in
Automotive,audio, DSP, DTV, EDA, Industrial Control, Mobile Handset, Power Management, Programmable Logic,RF,Video, and Wireless networking design. Check out the sites and let us know your thoughts.
|
Resource Links
|
|
|
HOW-TO: Enterprise Networking
|
Equivalent Results: A methodology to measure the effects of high-speed compression
Real-world examples demo the benefits of using appropriate compression (lower pin counts, lower power consumption, reduced board area, and lower system costs).
Compression/decompression tradeoffs for data networking and storage
Several design trade-offs to exist when building a high performance lossless data compression engine. Each of these trade-offs can vary the gate area of the end design greatly and have significant impact on the overall efficiency of the compressor (compression ratio).
System Clock Generators: PLL Synthesizer vs. Crystal Oscillator Clock--A comparison
Paul Shockman of On Semiconductor answers the question, "Should the new circuit board design or redesign use several crystal oscillator (XO) modules or a phase locked loop (PLL) synthesizer as its system clock source?" Read on for an in-depth comparison.
NSDL Weekend Reader: A collection of exceptional DesignLine articles--Volume 17
Encompassing change control, packet-processing/multicore processors, low power efficiency, RF mesh networks, OFDMA, crosstalk, and more, this Weekend Reader is sure to keep you scrolling screens in suspense.
Video codecs in SoCs using OCP-based programmable accelerator design
Video codecs involve a huge amount of data parallelism due to their block-based structure. Most computations are not performed on a single pixel, but on a block of pixels. Dedicated acceleration units with a wide data-path (16 x 16 x 8-bit = 2048-bit, for example) speed up the codec by up to three orders in magnitude compared to a pure software solution, facilitating lower clock rates. To support multiple standards, such as the VC-1 and H.264 video codecs, within a single SoC, considerable flexibility can be achieved by having programmable state machines instead of hardwired state machines.
Real-Time Operating Systems for DSP, part 2
Part 2 of this 8-part series introduces the concept of multitasking, and explains how an RTOS schedules tasks for execution.
Use digital signal controllers for robust power line communication--Part I
Power line communications provides a low-cost network with a ready-made infrastructure. Digital signal controllers provide the high level of processing needed to maintain robust signals on PLC networks, with performance overhead and on-chip peripherals that keep system costs down. See why.
A practical guide to low power efficiency measurements
This is a very practical article that teaches both seasoned and new engineers some measurement techniques of which they may not be aware. It is based on experience in the field with some of our customers.
MORE HOW-TO
|
|
|
| Tech Library |
¤ Looking for the appropriate Industry Association? This comprehensive, up-to-date list will take you to the right Web site for the help you need.
¤ Got a question about a standard? Here are direct links to resources detailing the industry's most important communications standards.
¤ Freshen up on technology, new and old, with these links to interesting and informative tutorials.
More from TechLibrary
|
|
|
