Video codecs in SoCs using OCP-based programmable accelerator design

The flexibility offered by OCP is of major importance for the design of programmable accelerators as they have to be integrated with other off-the-shelf and custom IP into sub-systems (e.g. video-subsystem) which again will be part of an even larger platform.

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Figure 5: CoWare ESL Design Solution

In order to explore, implement and verify the programmable accelerator in the platform context, OCP interfaces are generated on multiple abstraction levels. Processor Designer expands into CoWare's SystemC-based ESL design solution, allowing for the creation of virtual platforms used for hardware and software development. For the purpose of architecture exploration as well as software development, a SystemC instruction-set simulator (ISS) encapsulation with transaction-level OCP interfaces can be generated (TL2). This allows for the creation of fast and accurate virtual platforms employing one or more programmable accelerators and other IP (processors, peripherals, interconnect, etc.). Throughput and latency exploration is enabled, as well as early software development.

The CoWare ESL design solution also provides a seamless flow from exploration down to HDL implementation for the Programmable Accelerator design. A Verilog or VHDL model with pin-level OCP master interfaces (TL0) can be generated and co-simulated in the sub-system context for verification purposes. Additionally, the generated RTL can be taken through standard EDA synthesis tools for rapid FPGA prototyping and final implementation.

About the author
Achim Nohl received his degree in Electrical Engineering from the Institute for Integrated Signal Processing Systems at the University of Technology in Aachen, Germany in 2000. As a Ph.D. student at the same institute, he has published more than 10 technical papers and is the principal author of a publication about fast and flexible instruction-set simulation which received the Design Automation Conference (DAC) Best Paper Award in 2002. In 2002, Mr. Nohl worked at LISATek, Inc. as an architect of the LISA language-based processor design technology. From 2003 to 2005 he has worked as an engineering manager for the CoWare Processor Designer (LISATek) product line. Recently, Mr. Nohl moved into a Solution Specialist role with focus on Design and Modeling of Programmable Architectures at CoWare. He can be reached at achim@coware.com.

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