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Welcome to our DesignLine network of web communities. On these sites, we provide practical how-to technical information for engineers and engineering managers involved in
Automotive,audio, DSP, DTV, EDA, Industrial Control, Mobile Handset, Power Management, Programmable Logic,RF,Video, and Wireless networking design. Check out the sites and let us know your thoughts.
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Resource Links
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HOW-TO: IP Networking
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HD multi-room video distribution over IP-based home and commercial networks
Challenges using TCP/IP to distribute HD video include Bandwidth, lost packets, synchronization of signal distribution, and backwards / forwards compatibility. How NetStreams overcomes these hurdles to distribute multiple 1080p video streams.
Delivering outstanding video experiences over IP networks
Imagine you run a company that builds cars. You've been building cars for decades, and you've mastered the practice. Then one day, your company's board of directors decides that from now on, you're going to make jet planes instead. Even though you've never attempted anything like this before. This is what traditional wireline service providers around the world are facing right now as they make the transition from basic voice and data services to consumer video.
Tip of the Week: Correcting soft errors can't be an afterthought
To ensure the highest network QoS and compliance with service level agreements, the ternary content-addressable memory (TCAM) must use up-to-date error correction code (ECC) techniques. Here they are.
Signal integrity approaches meet the multi-Gbps design challenge
Understand how modeling and signal integrity can minimize problems of multi-Gbps data links
Transition IPv6 seamlessly in embedded systems
Here's an overview of IPv6 and an introduction to possible transition methods, complete with the implications of transition on an embedded system.
The challenges of next-gen multicore networks-on-chip systems: Part 6
In the sixth in a seven part series based on their book "Networks On Chips," Luca Benini and Giovanni De Micheli describe the architectural, programming and debug challenges of nextgen multicore networks-on-chips. This week: Communications-exposed programming.
Advanced interconnects drive intelligent vision applications: Part 1
Platform-centric methodology enables decoupling IP cores for parallel engineering with data flow design, early architecture exploration of data flows to characterize processor performance, and isolation of chip areas for rapid re-engineering of derivatives and updates.
Tip of the week: Net-interface accelerators can help or hinder
In some circumstances, the use of complex acceleration features can actually harm performance, system integrity and security.
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¤ Looking for the appropriate Industry Association? This comprehensive, up-to-date list will take you to the right Web site for the help you need.
¤ Got a question about a standard? Here are direct links to resources detailing the industry's most important communications standards.
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