Tip of the Week: Increase mobile multimedia quality--don't fry the battery

Because the multimedia data stream must be transferred from the baseband processor to the application processor, the performance problem now shifts to the interconnect between the two processors. Historically, there have been relatively few interconnect options. Of course, the designer could use one of the various embedded interfaces found on the processors, such as a UART, I2C, and USB. These low cost, low pin-count interfaces may have sufficed in second-generation handsets, but are completely inadequate in third-generation handsets, which must process multimedia with very high performance, yet a very low battery drain.

In recent years, asynchronous dual-port RAMs have delivered more-or-less adequate performance at an acceptable power drain--but for relatively low quality multimedia reproduction. These devices provided data rates comparable to high-speed USB without excessive battery drain. However, their long cycle times, the inefficiencies that stem from their asynchronous architecture, and the high pin-count associated with non-multiplexed interfaces, force designers to seek an alternative that can endure well into the next-generation of cellular technology.

A mobile multimedia interconnect that has been developed in close cooperation with leading handset and processor manufacturers cracks these problems. It uses a synchronous architecture that yields cycle times approximately 3x faster than asynchronous dual-port RAMs, and that--together with an internal counter--enables a data burst mode that eliminates the 50% inefficiency caused by the address-data-address-data scheme used in asynchronous address-data multiplex (ADM) interconnects. The net result is a 6X bandwidth improvement over asynchronous ADM devices. The interconnect has also been power-optimized, drawing 40% less operating current than the asynchronous dual port RAM approach. The combination of fewer and faster clock cycles with the significantly lower operating current results in a 90% lower battery drain. And that is independent of the type or size of the data being transferred.

Moreover, the interconnect's ADM interface consumes approximately 50% fewer pins than non-multiplexed solutions. It also liberates GPIO pins on the processors by deploying 8 dynamically programmable GPIO extender pins. These pins allow the interconnect to assume monitor and control responsibilities that would otherwise be undertaken by the processors, enabling the processor to be used for even more value added functions. In total, the mobile multimedia interconnect liberates more than 20 pins on the processors that can then be used to implement differentiating functionality.

Finally, the new interconnect's ADM interface maintains the modular nature of the dual-processor architectures, which is why it is fast becoming a de facto interface standard supported by handset processor manufacturers. The new interconnect also supports the traditional non-multiplexed interface, enabling it to interface with both current and legacy processors. This affords designers the freedom to mix and match both processors and processor manufacturers to meet a broad range of requirements.

Wireless handset designers must make many trade-offs to deliver the requisite value added functionality in the desired form factor, at the right performance, and with a battery drain that doesn't appreciably affect talk time and battery life. These trade-offs have a direct impact on the competitiveness of the handset. As more and more functions are included into wireless handsets and an even greater premium is placed on performance, power consumption, and pin-count, the mobile multimedia interconnect's ability to address all of these requirements with minimal impact on component price and board space offers high end handset designers are clear competitive advantage.

About the Author
Casey Springer is a senior product marketing engineer responsible for providing technical, tactical and strategic support to IDT customers and field sales engineers in Japan and Asia Pacific. Springer joined IDT in 2000 after graduating from Santa Clara University where he earned his bachelor of science degree in engineering physics with an emphasis in solid state physics. Since joining IDT, Springer has managed several new product introductions, has published multiple technical articles, and co-authored multiple patents. He can be reached at: casey.springer@idt.com