FACE-OFF Cisco/Cortina challenge interconnect industry

San Jose, Calif. -- In a surprise move, Cisco Systems Inc. and startup Cortina Systems Inc. will release an interconnect protocol today that they hope will be broadly used to link communications chips at data rates of 20 Gbits/second and beyond. But their Interlaken technology will be incompatible with a similar effort in a late stage of development at the Network Processing Forum, a group of about 30 silicon and systems developers.

The clash comes at a time when several initiatives are chasing multigigabit chip-to-chip links. Where Interlaken and NPF's Scalable-SPI spec are packet interfaces designed for a communications system's data plane, the other efforts--including RapidIO, PCI Express and HyperTransport--are typically aimed at control plane applications. The upshot of all those efforts will be a migration over the next few years from today's individual 1- to 2.5-Gbit/s serial-lane interconnects to far speedier links.

Engineers at Cisco saw that the 10-Gbit/s System Packet Interface-4.2, which requires 80 pins, could not keep pace with the rise of 10-Gbit Ethernet switches and systems using 80-Gbit/s or faster backplanes. "In our road map discussions with vendors, this problem kept cropping up," said Mark Gustlin, a technical lead in Cisco's Service Provider Routing Group.

More than a year ago, engineers from Cisco and Cortina found they were both working on a similar packet interface and decided to collaborate. The result is Interlaken, a pro- tocol for migrating the logical structures of SPI-4.2 onto a serdes transport based on the Optical Internetworking Forum's Common Electrical Interface standard. Using a 6.25-Gbit/s serdes, Interlaken slashes pin counts to just eight for a 10-Gbit/s link.

The spec acts as a framework that engineers can employ over serdes running from 3.125 to 10 Gbits/s across any number of parallel lanes. It could be used to connect a network processor with framer, traffic-management and port-aggregation chips on a line card, or to link those chips to a system backplane.

That's very similar to the Scalable-SPI spec the Network Processing Forum has been working on since June 2004. NPF started the SSPI effort as part of a collaborative agreement with the Optical Internetworking Forum (OIF), a broader group of about 80 carriers and OEMs.

About eight chip makers are going through what could be a final cleanup phase of the SSPI spec, though no exact release date has been set. Because it is still under development, details of SSPI remain under nondisclosure.

The good news is that the Interlaken and SSPI principals have just begun talking to each other, although it is too early to tell what may come of the discussions. The two sides are likely to find a number of interoperability issues as they take a detailed look at each other's specs.

Encoding split
To enhance system reliability, Cisco and Cortina chose a nonstandard 64B/67B encoding scheme that breaks compatibility with the 64B/66B approach. The latter is used in existing 10G Ethernet and framer chips and was adopted by SSPI.

"The extra bit allows us to more closely control dc balance," said Cisco's Gustlin. "In addition, we use a different scrambler than the standard 64/66 scrambler in order to prevent error multiplication.

"These changes make [Interlaken] incompatible with standard 64/66."

The encoding approach enables other capabilities. An inversion feature can flip the bits in a channel that has been determined to be in or near an error state. Interlaken also supports a MetaFrame feature that can shut down a lane that is failing and set up a redundant pathway.

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