QDR SRAM and RLDRAM: A comparative analysis

Choosing the right memory solution is pivotal to ensuring that the memory bandwidth is not a bottleneck on the throughput of an application. This article discusses memory solutions suitable for networking—specifically, Quad Data Rate Static RAM (QDR SRAMs) and Reduced Latency Dynamic RAM (RLDRAM)—and compares them in relation to the applications they are best suited for.

The evolution of networking SRAMs
Standard synchronous SRAMs, the earliest mainstream synchronous SRAMs, were ideal for cache applications. However, despite their extensive use, they were not suited for networking applications that dictated a balanced READ/WRITE profile. A READ operation followed immediately by a WRITE operation results in a contentious state on the data bus.

The only workaround for the bus contention was to introduce "wait" or "no operation" (NOP) cycles to accommodate for bus turnaround. But these wait cycles affected bus utilization resulting in underutilization of bandwidth. Because bandwidth utilization is a key factor, these synchronous SRAMs were not ideally suited for such networking applications.

Addressing the bus contention problem let to the development of No Bus Latency (NoBL), also known as Zero Bus Turnaround (ZBT), SRAMs. These SRAMs contained data registers in the periphery to pipeline the READ and WRITE operations, thereby eliminating the "wait" cycles and achieving peak bus utilization. However, with line rates reaching the order of tens of gigabits per second, it was necessary to address speed, bandwidth, and interface-related bottlenecks. Several applications emerged that not only demanded faster operation, but also required simultaneous READ and WRITE operations to the memory.

Although originally well suited for networking architectures, the NoBL SRAMs were unable to keep up with performance requirements. Hence, the development of a new generation of networking memories—the QDR/DDR family of SRAMs—to meet speed, density, and bandwidth requirements of today's networking applications.

The QDR/DDR family of SRAMs
QDR and QDR-II SRAMs, the latest generation of synchronous SRAMs, were developed by such companies as Cypress, Renesas, IDT, NEC, and Samsung, that make up the QDR consortium. This family of network SRAMs, along with Double Data Rate (DDR) and DDR-II SRAMs, provides complete memory solutions for any networking system.

QDR and QDR-II SRAMs come in speeds up to 300 MHz and beyond and densities of 9 Mb to 72 Mb, with future expansion of up to 288 Mb and beyond. QDR and QDR-II SRAMs feature separate ports for both READ and WRITE operations, eliminating bus contention. The double data rate interface on these ports—data is written to or read from the SRAM on both edges of the clock— essentially doubles the bandwidth of each pin when compared to other SRAMs. The combination of having separate input and output ports and DDR interfaces on these ports provides a four-fold increase in overall bandwidth compared to earlier synchronous SRAMs.

DDR and DDR-II SRAMs belong to the same family as QDR SRAMs, and are similar to the QDR and QDR-II SRAMs, with a major difference being that DDR and DDR-II SRAMs do not have separate read and write ports. While QDR SRAMs perform both READ and WRITE operations simultaneously, DDR devices can perform only READ or WRITE, but not both at a given time.

Several features make the QDR family of SRAMs ideal for high-speed networking applications, including:

• Output Clocks: In addition to input clocks K and K#, a pair of output data clocks, C and C# can be used to synchronize data from the SRAM. The use of these output clocks is optional. In single clock mode option, data is synchronized to the input clocks.
• Programmable Output Impedance: QDR SRAMs are equipped with programmable impedance circuitry that adjusts output driver strength to match the impedance of the transmission line. Matched impedance improves the signal integrity of the device.
• Echo Clocks: These SRAMs generate a pair of output clocks, CQ and CQ# that closely match the data (edge-aligned with the data). Thus, they serve as output clocks from the SRAM used for latching the output data into the controller. The echo clocks feature is available in QDR-II, DDR, and DDR-II products (not offered in QDR-I).

The following section discusses the Reduced Latency DRAM (RLDRAM), a family of DRAM memories used in networking applications.

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